Search - vhdl core

[VHDL-FPGA-Verilog] can

Description: can IP CORE .VERY GOOD AS A STUDY FILE-can IP CORE. VERY GOOD AS A STUDY FILE
Platform: | Size: 98304 | Author: lijun | Hits:

[Documents] encog-core-1.1.0

Description: VHDL制作的ann的code，希望大家可以用来作为参考-VHDL produced ann of the code, hope that can be used as a reference
Platform: | Size: 3530752 | Author: Yaojun zhang | Hits:

[VHDL-FPGA-Verilog] PIC

Description: 一个PIC单片机内核的VHDL实现，包含VHDL源码，说明文档-A PIC Singlechip realize VHDL core, including the VHDL source code, documentation
Platform: | Size: 39936 | Author: hhl | Hits:

[Other] VHDL_Core_for_1024_Point_Radix_4_FFT_Computation.

Description: This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx庐 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
Platform: | Size: 456704 | Author: alex | Hits:

[VHDL-FPGA-Verilog] jiaotongdeng

Description: 交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现-VHDL core
Platform: | Size: 401408 | Author: DAVID | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[SCM] 8051-core

Description: mcu8051 CPU FPGA VHDL software
Platform: | Size: 52224 | Author: 房有定 | Hits:

[VHDL-FPGA-Verilog] dianzishejishili

Description: 电子系统设计实例设计语言VHDL 实验仪器杭州康芯gw48eda 开发系统-Examples of electronic system design languages VHDL core experimental apparatus gw48eda Hangzhou Culture Development System
Platform: | Size: 3767296 | Author: familymxk | Hits:

[VHDL-FPGA-Verilog] 15-IP-core

Description: 15个免费的IP核 IP核源代码 -15 IP cores
Platform: | Size: 4579328 | Author: chris | Hits:

[VHDL-FPGA-Verilog] vhdl-arm-core

Description: 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used to open quartus2 simulation software.
Platform: | Size: 41984 | Author: 杨帆 | Hits:

[VHDL-FPGA-Verilog] vhdl-JPEG-enc

Description: JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
Platform: | Size: 796672 | Author: mahmoud | Hits:

[VHDL-FPGA-Verilog] pciug159

Description: XILINX ISE生成PCI-CORE时产生的用户文档,帮助编写PCI通信用户逻辑,非常有用-XILINX ISE generation PCI-CORE generated user documentation to help users prepare PCI communication logic, a very useful
Platform: | Size: 1374208 | Author: 田杰 | Hits:

[VHDL-FPGA-Verilog] vhdl-MIPS

Description: Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
Platform: | Size: 4330496 | Author: ak | Hits:

[Software Engineering] acceldsp1

Description: this the documentation of accel dsp software for dsp matlab to vhdl core
Platform: | Size: 118784 | Author: ashkan | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[VHDL-FPGA-Verilog] FT2232H_USB_Core

Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput. For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf" Included: VHDL core, NIOS test application, PC test application
Platform: | Size: 6144 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] 5-ge-ram-core

Description: 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，因为写得太好了，后被ARM公司封杀~~这里是目前我能找到的最终版本了~ Core_arm_VHDL.rar VHDL语言实现的arm内核，可以在http://www.opencores.org/project,core_arm下载到，不过还不是非常完整，有些小bug ARM7_VHDL.rar Ruslan Lepetenok用VHDL写的arm内核，也非常不错-5 ram nuclear, arm6_verilog, arm7_verilog_1, arm7_VHDL, Core_arm_VHDL, nnARM01_11_1_3 arm6_verilog.rar arm of a simple kernel, verilog to write, a bit messy arm7_verilog_1.rar J. Shin arm7 use verilog to write the core of well-structured, easily understandable nnARM01_11_1_3 . zip.zip nnARM open source projects, National Defense University cattle ShengYu Shen wrote, the original on the opencores, because so good, and after the ban, ARM ~ ~ Here is the final version I could find out ~ Core_arm_VHDL.rar VHDL language of the arm core, you can http://www.opencores.org/project, core_arm downloaded to, but not very complete, and some small bug ARM7_VHDL.rar Ruslan Lepetenok written in arm with VHDL core, but also very good
Platform: | Size: 1152000 | Author: YeZiqiang | Hits:

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